Conventional three-dimensional semiconductor integrated circuit devices are known in which, two or more wafers are layered vertically, and the wafers are electrically connected to each other in the vertical direction by through-wiring (see, for example, Japanese Patent Laid-Open Publication No. 11-261000).
According to the method for manufacturing a three-dimensional semiconductor integrated circuit device described in the 11-261000 publication, an upper LSI wafer layer and a lower LSI wafer layer are prepared, and a trench (deep groove) is formed in the upper LSI wafer layer, after which a vertical interconnector (through-wiring) used for wiring is embedded in the trench. A bump is then formed at an end of the vertical interconnector, and the upper LSI wafer layer is affixed to the lower LSI wafer layer via the bump. An insulating adhesive is finally injected between the upper and lower LSI wafers affixed to each other only by the bump.
Following is a description of drawbacks relating to the “sequence of steps” in the conventional method for manufacturing a three-dimensional semiconductor integrated circuit device.
In the case of the method for manufacturing a three-dimensional semiconductor integrated circuit device disclosed in the abovementioned reference, the sidewalls of each trench are first oxidized to provide an insulation film, and then a metal is deposited into the trenches to complete the through-wiring. A semiconductor integrated circuit that includes a transistor and other elements is then formed.
However, when through-wiring and a semiconductor integrated circuit are formed according to a sequence of steps such as the one described above, high temperatures of about 800 to 1000° C. occur in the process of manufacturing the transistor and other elements. Therefore, the metal constituting the through-wiring formed in the previous stage is scattered into the transistor region by this high-temperature process, possibly resulting in metal contamination of the transistor region. This metal contamination causes fluctuation of the electrical characteristics of elements in regions other than that of the through-wiring.
Drawbacks also occur when the through-wiring formed out of metal is completed before or during formation of the transistor, in that only an extremely limited range of materials such as titanium, nickel, cobalt, tungsten, and the like can be used as the metal, for the through-wiring without adversely affecting the transistor characteristics.
In order to avoid the abovementioned drawbacks caused by the through-wiring being composed of a metal, the through-wiring may be formed by embedding, a polysilicon or other nonmetal conductive substance in the trenches instead of a metal.
However, polysilicon and other nonmetal conductive substances have higher resistance than metals. Using a substance with higher resistance than metal to form the through-wiring in this manner leads to drawbacks of increased power consumption and reduced operating speed in a device in which the semiconductor integrated circuit is used.
A method may also be used in which the sequence of steps is fundamentally changed in order to overcome all of the drawbacks described above. For example, an insulation film may be formed by high-temperature oxidation of the sidewalls of the trench after the semiconductor integrated circuit is formed, and the through-wiring may be completed by embedding a metal into the trench.
In this type of method, however, since the step for forming the insulation film on the trench sidewalls involves processing at high temperatures of approximately 800° C. or higher, ion implantation and other processes induce re-diffusion of the impurity (dopant) region formed in the transistor region of the semiconductor integrated circuit. This phenomenon also causes the transistor characteristics to fluctuate.
For a trench having a low aspect ratio, it is possible to form an insulation film on the sidewall without performing high-temperature, oxidation treatment. However, the formation of through-wiring that utilizes a low-aspect-ratio trench severely reduces the degree of integration of the semiconductor integrated circuit device, and thus introduces drawbacks from another perspective.
A combination in which the steps are arranged in the following sequence is considered in order to overcome all of the abovementioned drawbacks at once: “trench formation”→“sidewall oxidation”→“transistor formation”→“formation of through-wiring by metal filling.” In this case, however, lithography processing, washing that accompanies resist removal, and other types of processing are performed while the trench is still in an open state. Therefore, the photoresist, developing solution, and other substances used in these processes are left behind in the trench.
It may be possible to provide a step for forming a film cap of an oxide such as SiO2 on the open portion of each trench, and a step for subsequently removing the cap in order to prevent the photoresist and other substances from remaining in the trenches. However, these steps are extremely difficult to provide technologically, and providing these steps significantly alters the conditions for flattening the top of the semiconductor substrate, thereby creating new drawbacks.
The drawbacks of the prior art relating to “alignment tolerance” will next be described. Wiring is patterned by exposure treatment in a method for manufacturing a semiconductor integrated circuit device. Since misalignment occurs during patterning, devices are generally designed to maintain an “alignment tolerance (margin)” in the portions connected by wiring.
In the manufacturing method described in the previously mentioned Japanese Laid-open Patent Application No. 11-261000, an insulating layer made of SiO2 or the like must be formed around the ends of each of a plurality of units of through-wiring arranged at high density while maintaining alignment tolerance. This method therefore has drawbacks in that a technique of high-precision alignment is required in order to maintain the alignment tolerance. Furthermore, maintaining alignment tolerance around the ends of the through-wiring creates drawbacks in that the substantial surface area of the open portion of the through-wiring is decreased. This leads to the further drawback of increased resistance in the through-wiring portion.